1. Field of the Invention
The present invention relates to a “chip-on-board” (COB) semiconductor assembly and, more particularly, to a method and apparatus for reducing stress resulting from lodging of filler particles present in encapsulant and glob top materials between a surface of a semiconductor die and a corresponding surface of a semiconductor substrate and for visual inspection of the attachment of the semiconductor die to the semiconductor substrate with the use of tape attachment material.
2. State of the Art
Definitions: The following terms and acronyms will be used throughout the application and are defined as follows:
COB—Chip-On-Board: The techniques used to attach a semiconductor die to a semiconductor substrate, such as a printed circuit board.
Glob Top: A glob of encapsulant material (usually epoxy or silicone or a combination thereof) surrounding a semiconductor die or portion thereof in a COB assembly.
Wire Bonding: Conductive wires attached between a semiconductor die and a circuit board or leadframe to form an electrical connection therebetween.
TAB—Tape Automated Bonding: Conductive traces are formed on a dielectric film such as a polyimide (the structure also being termed a “flex circuit”), and the film is precisely placed to electrically connect a semiconductor die and a circuit board or leadframe through the conductive traces. Multiple connections are simultaneously effected.
FIGS. 14 and 15 illustrate exemplary COB assemblies 200 each comprising a semiconductor die 202 back-bonded with an adhesive layer 204 to a semiconductor substrate 206. The semiconductor die 202 is in electrical communication with the semiconductor substrate 206 through electrical elements extending between bond pads 208 on the semiconductor die 202 and traces 212 on the semiconductor substrate 206. The electrical elements are generally bond wires 214, as illustrated in FIG. 14, or TAB connections 216, as illustrated in FIG. 15.
In wire bonding, as illustrated in FIG. 14, a plurality of bond wires 214 is attached, one at a time, to each bond pad 208 on the semiconductor die 202 and extends to a corresponding lead or trace 212 on the semiconductor substrate 206. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding—using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding—using a combination of pressure, elevated temperature, and ultrasonic vibration bursts.
With TAB, as illustrated in FIG. 15, TAB connectors 216 (generally metal leads carried on an insulating tape, such as a polyimide) are attached to each bond pad 208 on the semiconductor die 202 and to a corresponding lead or trace 212 on the semiconductor substrate 206.
An encapsulant 218, such as a plastic resin, is generally used to cover the bond wires 214 (FIG. 14) and TAB connectors 216 (FIG. 15) to prevent contamination, aid mechanical attachment of the assembly components, and increase long-term reliability of the electronics with reasonably low-cost materials.
An exemplary technique of forming the encapsulant 218 is molding and, more specifically, transfer molding. In the transfer molding process (and with specific reference to COB die assemblies), after the semiconductor die 202 is attached to the semiconductor substrate 206 (e.g., FR-4 printed circuit board) and electrical connections made (by wire bonding or TAB) to form a die assembly, the die assembly is placed in a mold cavity in a transfer molding machine. The die assembly is thereafter encapsulated in a thermosetting polymer which, when heated, reacts irreversibly to form a highly cross-linked matrix no longer capable of being re-melted. Additionally, another common manner of forming encapsulants for COB assemblages is “glob top” polymeric encapsulation. Glob top encapsulation can be applied by dispensing suitably degassed material from a reservoir through a needle-like nozzle onto the die assembly.
The thermosetting polymer of transfer molding generally is comprised of three major components: an epoxy resin, a hardener (including accelerators), and a filler material. Other additives such as flame retardants, mold release agents and colorants are also employed in relatively small amounts. Furthermore, glob top encapsulation can comprise a non-linear thixotropic material that also includes fillers to achieve the desired degree of thixotropy.
While many variations of the three major components are known in the art, the present invention focuses on the filler materials employed and their effects on the active semiconductor die surfaces and corresponding semiconductor substrate surfaces.
Filler materials are usually a form of fused silica, although other materials such as calcium carbonates, calcium silicates, talc, mica and clays have been employed for less rigorous applications. Powdered fused quartz is currently the primary filler used in encapsulants. Fillers provide a number of advantages in comparison to unfilled encapsulants. For example, fillers reinforce the polymer and thus provide additional package strength, enhance thermal conductivity of the package, provide enhanced resistance to thermal shock, and greatly reduce the cost of the polymer in comparison to its unfilled state. Fillers also beneficially reduce the coefficient of thermal expansion (CTE) of the composite material by about fifty percent in comparison to the unfilled polymer, resulting in a CTE much closer to that of the silicon or gallium arsenide die. Filler materials, however, also present some recognized disadvantages, including increasing the stiffness of the plastic package, as well as the moisture permeability of the package.
Two problems encountered in transfer molding are bond wire sweep and connection detachment. Bond wire sweep occurs in wire bonded packages wherein the encapsulant material, which is injected into the mold under pressure, deforms the bond wires which can cause shorting. Connection detachment can occur in either TAB connections 216 or bond wires 214, wherein stresses created by the pressurized encapsulant material result in the detachment of the TAB connections 216 or bond wires 214 from either the bond pad 208 or the trace 212.
To alleviate this problem and to reduce the thickness of the semiconductor assembly, as illustrated in FIG. 16, a technique of face-down attachment of a semiconductor die 232 onto a semiconductor substrate 234 with an adhesive tape 236 has been developed. With this technique, the semiconductor substrate 234 has an opening 238 therethrough with electrical connections 240 (shown as bond wires) extending through the opening 238 to connect the bond pads 242 on an active surface 262 of the semiconductor die 232 to the traces 244 on an active surface 250 of the semiconductor substrate 234. The adhesive tape 236 used in these assemblies is generally narrow and does not extend to an edge 246 of the semiconductor die 232, resulting in exterior voids 248, and does not extend to an edge 252 of the opening 238, resulting in interior voids 254. The opening 238 is filled and the electrical connections 240 are covered with a glob top material 256 injected into the opening 238, as shown in FIG. 17. Thus, the electrical connections 240 are protected from bond wire sweep and connection detachment. As shown in FIG. 18, an encapsulant material 258 is molded over the semiconductor die 232.
Unfortunately, a significant disadvantage of using glob top materials and encapsulant materials having filler particles is the potential for damage to the active surface 262 of the semiconductor die 232 and/or a back surface 264 of the semiconductor substrate 234 resulting from the lodging or wedging of filler particles 266 between the semiconductor die active surface 262 and the semiconductor substrate back surface 264, as shown in FIGS. 19 and 20.
As shown in FIG. 19, which is an enlarged view of the inset 19 of FIG. 17, if filler particles 266 are used in the glob top material 256, the filler particles 266 may be jammed between the semiconductor die active surface 262 and the semiconductor substrate back surface 264 within the interior void 254. Furthermore, as shown in FIG. 20, which is an enlarged view of the inset 20 of FIG. 18, if filler particles 266 are used in the encapsulant material 258, the filler particles 266 may also be jammed between the semiconductor die active surface 262 and the semiconductor substrate back surface 264 within the exterior void 248 due to non-uniform polymer flow patterns and flow imbalances of the encapsulant material 258 in the mold cavity during transfer molding. The jammed filler particles 266 place the semiconductor die active surface 262 and the semiconductor substrate back surface 264 under residual stress at the points of contact with the jammed filler particles 266. The particles may then damage or crack the semiconductor die active surface 262 and/or the semiconductor back surface 264 when the assembly is stressed (i.e., mechanically, thermally, electrically, etc.) during post-encapsulation handling and testing. This damage can result in failure of the semiconductor assembly, alteration of the performance characteristics, and/or, if the damage is not immediately detected, unanticipated shortening of device life.
While it is possible to employ a lower volume of filler particles 266 in the encapsulant material 258 to reduce the potential for the filler particles 266 lodging or wedging, a drastic reduction in filler volume raises costs of the polymer to unacceptable levels. Additionally, while the size of the filler particles 266 may be reduced to reduce the potential for the filler particles 266 lodging or wedging, currently available filler technology imposes certain limitations as to practical beneficial reductions in particle size and in the shape of the filler particles 266. Furthermore, while it is desirable that filler particles 266 be of generally spherical shape, it has thus far proven impossible to eliminate non-spherical flakes or chips which when jammed between the semiconductor die active surface 262 and the semiconductor back surface 264 are more prone to damage the semiconductor die active surface 262 and/or the semiconductor back surface 264. Moreover, an underfilling could be used to seal the interior voids 254 and the exterior voids 248. However, such underfilling would be prohibitively expensive.
The problem of semiconductor assembly damage due to jammed filler particles 266 in association with assembly stressing (i.e., mechanically, thermally, electrically, etc.) during post-encapsulation handling and testing will continue to worsen as ongoing advances in design and manufacturing technology provide increasingly thinner conductive, semiconductive, and dielectric layers. The resulting semiconductor assemblies will be more susceptible to stressing due to the minimal strength provided by the minute widths, depths and spacings of the constituent elements of the semiconductor assemblies. Thus, with increasing stress susceptibility, the semiconductor assemblies are more prone to damage from jammed filler particles 266.
In addition to solving the problems associated with filler particle 266 lodging and damage, it is desirable to improve the ability to visually inspect for proper attachment of the semiconductor die 232 to the semiconductor substrate 234 (i.e., inspect for misaligned or missing adhesive tape 236). Prior art COB die assemblies have been unsuccessful, not only in preventing damage due to the filler particles 266, as explained above, but also in providing an eye point for enhanced visual inspection (generally by a computerized optical detection apparatus) of the proper attachment of the semiconductor die 232 to the semiconductor substrate 234 prior to encapsulation.
This lack of proper inspection is generally due to the use of narrow adhesive tape 236 which does not extend to an edge 246 of the semiconductor die 232, nor to an edge 252 of the opening 238, as shown in FIGS. 14–18 and as discussed above. The use of such narrow adhesive tape 236 makes visual inspection of the proper tape attachment extremely difficult, because inspection must be made by looking longitudinally between the semiconductor die 232 and the semiconductor substrate 234 along the respective attachment surfaces where spacing is microscopic. Visual inspection cannot be made looking vertically either (i.e., looking upward through the opening 238 or downward at the semiconductor substrate back surface 264) because the adhesive tape 236 is enclosed between the semiconductor die 232 and the semiconductor substrate 234. Furthermore, the use of narrow adhesive tape 236 also limits the contact surface area available for semiconductor die 232 to semiconductor substrate 234 adhesion and attachment.
Furthermore, it is desirable to increase or enhance the stability of the semiconductor assembly in order to reduce or eliminate localized stress failures occurring during encapsulation. These failures can cause subsequent cracking. Semiconductor assembly stability, in the past, has been approached from the perspective of improving adhesives employed with carrier films, rather than by sealing the gaps or spaces between the semiconductor substrate and the semiconductor die.
U.S. Pat. No. 5,733,800 issued Mar. 31, 1998 to Moden (“the Moden patent”) discloses a “leads over chip” (LOC) die assembly, wherein a seal between a leadframe and a die is created by underfill material introduced into and extending between the bonding location of the die and the edge of the die. However, the Moden patent relates to an LOC assemblage which utilizes a narrow tape segment and requires the added expense of introducing underfill material in between the leadframe and the semiconductor die in order to seal the gap or space proximate the tape segment. In addition, the use of LOC assemblages, as in the Moden patent, does not create the type of visual inspection problems discussed above and inherent in COB assemblages because tape segments can be viewed when looking between leads of the leadframe.
Additionally, U.S. Pat. No. 5,466,888 issued Nov. 14, 1995 to Beng et al. (“the Beng patent”) discloses a LOC semiconductor device utilizing an electrically insulating film interposed between the leads and the chip for strengthening adherence of the film to packaging material and to the chip. However, as with the Moden patent, the Beng patent relates to a LOC assemblage.
From the foregoing, the prior art has neither provided for visual die assembly inspection, nor recognized the stress phenomenon associated with encapsulant materials having filler particles with COB assemblies. Thus, it can be appreciated that it would be advantageous to develop a semiconductor assembly and a technique to fabricate the same which eliminate potential damage due to filler particles and allow for pre-encapsulation semiconductor die to semiconductor substrate attachment and sealing visual inspection.